XRT79L71_1 Datasheet, PDF (406/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2
(Address = 0x1F65)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User Cell Filter # 2 - Pattern Register - Byte 2 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit User Cell Filter
# 2 - Pattern Register -
Header Byte 2
TYPE
R/W
DESCRIPTION
Transmit User Cell Filter # 2 - Pattern Register - Header Byte
2:
The User Cell filtering criteria (for Transmit User Cell Filter # 2) is
defined based upon the contents of 9 read/write registers.
These registers are the four Transmit ATM Cell Processor Block
- Transmit User Cell Filter # 2 - Pattern Registers, the four Trans-
mit ATM Cell Processor Block - Transmit User Cell Filter # 2 -
Check Registers and the Transmit ATM Cell Processor Block -
Transmit User Cell Filter # 2 Control Register.
This READ/WRITE register, along with the Transmit ATM Cell
Processor Block - Transmit User Cell Filter # 2 - Check Register
- Header Byte 2 permits the user to define the User Cell Filtering
criteria for Octet # 2 of the incoming User Cell. The user will
write the header byte pattern (for Octet 2) that the user wishes to
use as part of the User Cell Filtering criteria, into this register.
The user will also write in a value into the Transmit ATM Cell
Processor Block - Transmit User Cell Filter # 2 - Check Register
- Header Byte 2 that indicates which bits within the first octet of
the incoming cells are to be compared with the contents of this
register.
Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3
(Address = 0x1F66)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User Cell Filter # 2 - Pattern Register - Byte 3 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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