XRT79L71_1 Datasheet, PDF (67/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
0
Transmit Level 2 Mode
TYPE
R/W
DESCRIPTION
Transmit POS-PHY Level 2, Packet Mode:
This READ/WRITE bit-field along with Bits 1 and 0
(Transmit_Mode[1:0]) within the Transmit POS-PHY Interface -
Transmit Control Register - Byte 1 permits the user to configure
the Transmit POS-PHY Interface block to operate in any of the
following modes.· The Level 2, Packet Mode· The Level 2,
Chunk Mode· The Level 3, Packet Mode· The Level 3, Out-of-
Band, Chunk Mode· The Level 3, In-Band, Chunk ModeThe fol-
lowing table presents the relationship between these three bits,
and the corresponding operating mode of the Transmit POS-
PHY Interface block.
Transmit
Mode[1:0]
00
01
10
11
11
Transmit
Level 2 Mode
Resulting Mode of Operation
0
Level 2, Chunk Mode
0
Level 3, Out-of-Band Chunk Mode
0
Level 3, In-Band Chunk Mode
0
Level 3, Packet Mode
1
Level 2, Packet Mode
A brief description of the Transmit POS-PHY Level 2 and 3
Modes are presented below.
If the Transmit POS-PHY Interface block is configured to
operate in the POS-PHY Level 2 Mode
If the Transmit POS-PHY Interface block is configured to operate
in the POS-PHY Level 2 Mode, then all of the following is true.
• When polling, the Receive POS-PHY Interface block will drive
the TxPPA output pin to the appropriate level (reflecting the
TxFIFO fill-status) within ONE TxPClk period (in lieu of two
TxPClk periods) after sampling a given POS-PHY Port
Address via the TxPAddr[4:0] input pins.
If the Transmit POS-PHY Interface block is configured to operate
in the POS-PHY Level 3 Mode
If the Transmit POS-PHY Interface block is configured to operate
in the POS-PHY Level 3 Mode, then all of the following are true.
• When polling, the Transmit POS-PHY Interface block will drive
the TxPPA output pin to the appropriate level (reflecting the
TxFIFO fill-status) within TWO TxPClk periods (in lieu of one
TxPClk periods) after sampling a given POS-PHY Port
Address via the TxPAddr[4:0] input pins.
Transmit POS-PHY Interface - Transmit Control Register Byte - 1 (Address = 0x0581)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Chunk_Size[2:0]/
TxFIFO_Packet_Fill_Level[2:0]
Transmit POS-PHY Data
Bus Width[1:0]
Transmit Mode[1:0]
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
X
X
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