XRT79L71_1 Datasheet, PDF (82/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
6
HDLC Controller Enable
Continued
5
HDLC CRC-32
TYPE
R/W
R/W
DESCRIPTION
In the Receive Direction
In the Receive Direction, the Receive High-Speed HDLC Con-
troller block will accept the payload data (within the incoming
DS3/E3 data-stream) from the Receive DS3/E3 Framer block.
As the Receive High-Speed HDLC Controller block receives this
incoming data, it will perform the following functions.
• It will flag any occurrence of the Flag Sequence octet, within
the incoming data-stream..
• It will locate the boundaries of the incoming HDLC frames.· It
will perform zero-unstuffing on the payload data (within each
incoming HDLC frame).
• It will compute and verify either the CRC-16 or CRC-32 value
(that is appended at the back-end of the outbound HDLC
Frame).
• It will output this incoming HDLC data to the System-Side
Terminal Equipment via a byte-wide output interface.
0 - Configures the XRT79L71 to operate in the Clear-Channel
Framer Mode (e.g., disables the Transmit and Receive High-
Speed HDLC Controller blocks).
1- Configures the XRT79L71 to operate in the High-Speed
HDLC Controller (e.g., enables the Transmit and Receive High-
Speed HDLC Controller blocks).
HDLC CRC-32:
This READ/WRITE bit-field permits the user to configure the
Transmit and Receive High-Speed HDLC Controller blocks to
handle either CRC-16 or CRC-32 values (at the back-end of
each HDLC frame), as described below.
If configured to handle CRC-16 values
If the XRT79L71 is configured to handle CRC-16 Values then all
of the following is true.
• The Transmit High-Speed HDLC Controller block will compute
and append a CRC-16 (2-byte) value to the back-end of each
Outbound HDLC frame.
• The Receive High-Speed HDLC Controller block will compute
and verify the CRC-16 value (which has been appended to the
back-end) of each incoming HDLC frame.
If configured to handle CRC-32 values:
If the XRT79L71 is configured to handle CRC-32 Values then all
of the following is true.
• The Transmit High-Speed HDLC Controller block will compute
and append a CRC-32 (4-byte) value to the back-end of each
Outbound HDLC frame.
• The Receive High-Speed HDLC Controller block will compute
and verify the CRC-32 value (which has been appended to the
back-end) of each incoming HDLC frame.
0 - Configures the XRT79L71 to handle CRC-16 values.
1 - Configures the XRT79L71 to handle CRC-32 values.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the High-Speed HDLC
Controller Mode.
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