XRT79L71_1 Datasheet, PDF (202/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
7-0
One_Second_Parity
Error Accum_MSB[7:0]
TYPE
R/O
DESCRIPTION
One Second Parity Error Accumulator Register - MSB:
These READ-ONLY bits, along with that within the One Second
Parity Error Accumulator Register - LSB combine to reflect the
cumulative number of Parity Errors that have been detected by
the Receive DS3/E3 Framer block, in the last One second accu-
mulation period. This register contains the Most Significant byte
of this 16-bit expression.
NOTES:
1. For DS3 applications, the register will reflect the
number of P-bit errors, detected within the last One
second accumulation period.
2. For E3, ITU-T G.751 applications, this register will
reflect the number of BIP-4 errors, detected within the
last One second accumulation period.
3. For E3, ITU-T G.832 applications, this register will
reflect the number of BIP-8 (B1 Byte) errors detected
within the last One second accumulation period.
One Second - Parity Error Accumulator Register - LSB (Address = 0x1171)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
One_Second_Parity_Error_Accum_LSB[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
BIT 1
R/O
0
BIT 0
R/O
0
BIT NUMBER
NAME
7-0
One_Second_Parity
Error Accum_LSB[7:0]
TYPE
R/O
DESCRIPTION
One Second Parity Error Accumulator Register - LSB:
These READ-ONLY bits, along with that within the One Second
Parity Error Accumulator Register - MSB combine to reflect the
cumulative number of Parity Errors that have been detected by
the Receive DS3/E3 Framer block, in the last One second accu-
mulation period. This register contains the Least Significant byte
of this 16-bit expression.
NOTES:
1. For DS3 applications, the register will reflect the
number of P-bit errors, detected within the last One
second accumulation period.
2. For E3, ITU-T G.751 applications, this register will
reflect the number of BIP-4 errors, detected within the
last One second accumulation period.
3. For E3, ITU-T G.832 applications, this register will
reflect the number of BIP-8 (B1 Byte) errors detected
within the last One second accumulation period.
193