XRT79L71_1 Datasheet, PDF (89/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
5
Change of AIS Defect
Condition Interrupt Status
4
Change of DS3 Idle
Condition Interrupt Status
3
Change of FERF/RDI
Defect Condition Inter-
rupt Status
2
Change of AIC State
Interrupt Status
1
Change of OOF Defect
Condition Interrupt Status
0
Detection of P-Bit Error
Interrupt Status
TYPE
RUR
RUR
RUR
RUR
RUR
RUR
DESCRIPTION
Change in AIS Defect Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
Change in AIS Defect Condition Interrupt has occurred since the
last read of this register as depicted below.
0 - The Change in AIS Defect Condition Interrupt has not
occurred since the last read of this register.
1 - The Change in AIS Defect Condition Interrupt has occurred
since the last read of this register.
Change in DS3 Idle Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
Change in DS3 Idle Condition interrupt has occurred since the
last read of this register.
0 - The Change in DS3 Idle Condition Interrupt has not occurred
since the last read of this register.
1 - The Change in DS3 Idle Condition Interrupt has occurred
since the last read of this register.
Change in FERF/RDI Defect Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
Change in FERF/RDI Defect Condition Interrupt has occurred
since the last read of this register.
0 - The Change in FERF/RDI Defect Condition Interrupt has not
occurred since the last read of this register.
1 - The Change in FERF/RDI Defect Condition Interrupt has
occurred since the last read of this register.
Change in AIC State Interrupt Status:
This RESET-upon-READ register bit indicates whether or not the
Change in AIC State interrupt has occurred since the last read of
this register.
0 - The Change in AIC State Interrupt has not occurred since the
last read of this register.
1 - The Change in AIC State Interrupt has occurred since the last
read of this register.
Change in OOF Defect Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
Change in OOF Defect Condition Interrupt has occurred since
the last read of this register.
0 - The Change in OOF Defect Condition Interrupt has not
occurred since the last read of this register.
1 - The Change in OOF Defect Condition Interrupt has occurred
since the last read of this register.
Detection of P-Bit Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of CP-Bit Error Interrupt has occurred since the last
read of this register.
0 - The Detection of CP-Bit Error Interrupt has not occurred
since the last read of this register.
1 - The Detection of CP-Bit Error Interrupt has occurred since
the last read of this register.
80