XRT79L71_1 Datasheet, PDF (58/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
3-2
Receive POS-PHY Data
Bus Width[1:0]
1-0
Receive Mode[1:0]
TYPE
R/W
DESCRIPTION
Receive POS-PHY Data Bus Width[1:0]:
These two READ/WRITE bit-fields permit the user to select/
specify the width of the Receive POS-PHY Data Bus. The fol-
lowing table presents the relationship between the contents
within these two bit-fields and the corresponding width of the
Receive POS-PHY Data Bus.
Receive POS-PHY Width of Receive
Data Bus Width[1:0] POS-PHY Data Bus
000
Inactive
001
Unused
010
16 - bits
011
8 - bits
R/W
NOTE: This configuration setting only applies to the Receive
POS-PHY Interface block, and does not apply to the
Transmit POS-PHY Interface block.
Receive POS-PHY Interface Mode[1:0]:
These two READ/WRITE bit-fields, along with Bit 0 (Receive
POS-PHY Level 2 Packet Mode) within the Receive POS-PHY
Interface - Receive Control Register Byte 2 (Address = 0x0500)
permit the user to configure the Receive POS-PHY Interface
block to operate in any of the following modes.
• Level 2 Packet Mode
• Level 2, Chunk Mode
• Level 3, Packet Mode
• Level 3, Chunk Mode
The following table presents the relationship between these
three bits and the corresponding operating mode of the Receive
POS-PHY Interface block.
Receive Mode[1:0]
00
01
10
10
Receive Level 2
Mode
X
X
0
1
Resulting Mode of
Operation
Level 2, Chunk Mode
Level 3, Chunk Mode
Level 3, Packet Mode
Level 2, Packet Mode
A brief description of the Receive POS-PHY Level 2 and Level 3
Modes are presented below.
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