XRT79L71_1 Datasheet, PDF (123/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
2
Detection of BIP-8 Error
Interrupt Status
1
Detection of Framing
Byte Error Interrupt Sta-
tus
0
Detection of PLD Type
Mismatch Interrupt Status
TYPE
RUR
RUR
RUR
DESCRIPTION
Detection of BIP-8 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of BIP-8 Error Interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate an interrupt anytime is detects a BIP-8 Error in the
incoming E3 data-stream.
0 - Indicates that the Detection of BIP-8 Error Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Detection of BIP-8 Error Interrupt has
occurred since the last read of this register.
Detection of Framing Byte Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of Framing Byte Error Interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate an interrupt anytime is detects an error in either the
FA1 or FA2 byte, within the incoming E3 data-stream.
0 - Indicates that the Detection of Framing Byte Error Interrupt
has NOT occurred since the last read of this register.
1 - Indicates that the Detection of Framing Byte Error Interrupt
has occurred since the last read of this register.
Detection of Payload Type Mismatch Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of Payload Type Mismatch Interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate an interrupt anytime it receives an E3 data-stream that
contains a RxPLDType[2:0] that is different from the RxPLD-
TypeExp[2:0] value.
0 - Indicates that the Detection of Payload Type Mismatch Inter-
rupt has NOT occurred since the last read of this register.
1 - Indicates that the Detection of Payload Type Mismatch Inter-
rupt has occurred since the last read of this register.
NOTE:
The user can obtain the contents of the most recently
received Payload Type by reading out the contents of
Bits 7 through 5 (RxPLDType[2:0]) within the Receive
E3 Configuration and Status Register # 1 - G.832
(Address = 0x1110).
Receive E3 LAPD Control Register - G.832 (Address = 0x1118)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxLAPD
Any
Unused
Receive
LAPD from
NR Byte
BIT 2
Receive
LAPD
Enable
R/W
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
BIT 1
Receive
LAPD
Interrupt
Enable
R/W
0
BIT 0
Receive
LAPD
Interrupt
Status
RUR
0
114