XRT79L71_1 Datasheet, PDF (364/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Payload Register (Address = 0x1F1F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Payload Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Idle Cell
Payload Byte[7:0]
TYPE
R/W
DESCRIPTION
Transmit Idle Cell Payload Byte [7:0]:
These READ/WRITE register bits permit the user to define the
value of the payload bytes of all Idle Cells that are generated and
transmitted by the Transmit ATM Cell Processor block.
NOTE: Each of the 48 payload bytes (within each outbound Idle
Cell) will be assigned the value that is written into this
register.
Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 1 (Address = 0x1F20)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Test Cell Header Byte 1 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Test Cell
Header Byte 1[7:0]
TYPE
R/W
DESCRIPTION
Receive Test Cell Header Byte 1:
These READ/WRITE register bits along with that in the Transmit
ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 2
through 4 permit the user to define the headers of test cells that
the Transmit Test Cell Generator will generate.
This particular register byte permits the user to define the con-
tents of Header Byte # 1.
NOTE: These register bits are only active if the Transmit Test
Cell Generator has been enabled.
355