XRT79L71_1 Datasheet, PDF (174/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
4-0
TxFAS_Error_Mask_Low
er[4:0]
TYPE
R/W
DESCRIPTION
TxFAS Error Mask Lower[4:0]:
These READ/WRITE bit-fields permit the user to insert bit errors
into the lower five bits, within the FAS (Framing Alignment Sig-
nal), within the outbound E3 data stream.
The Transmit E3 Framer block will perform an XOR operation
with the contents of these FAS bits, and this register. The results
of this calculation will be inserted into the lower 5 FAS bit posi-
tions within the Outbound E3 data stream. For each bit-field
(within this register) that is set to "1", the corresponding bit,
within the FAS will be in error.
NOTE: For normal operation, the user should set this register to
0x00.
Transmit E3 BIP-4 Mask Register - G.751 (Address = 0x114A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
TxBIP-4_Mask[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
R/W
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-4
Unused
R/O
3-0
TxBIP-4_Mask_[3:0]
R/W TxBIP-4 Error Mask[3:0]:
These READ/WRITE bit-fields permit the user to insert bit errors
into the BIP-4 bits, within the outbound E3 data stream.
The Transmit E3 Framer block will perform an XOR operation
with the contents of the BIP-4 bits, and this register. The results
of this calculation will be inserted into the BIP-4 bit positions
within the Outbound E3 data stream. For each bit-field (within
this register) that is set to "1", the corresponding bit, within the
BIP-4 will be in error
NOTE: For normal operation, the user should set this register to
0x00.
TRANSMIT E3, ITU-T G.832 RELATED REGISTERS
Transmit E3 Configuration Register - G.832 (Address = 0x1130)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused TxDL in NR Reserved
TxAIS
Enable
TxLOS
Enable
R/O
R/O
R/O
R/W
R/O
0
0
0
0
0
BIT 2
TxMA Rx
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
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