XRT79L71_1 Datasheet, PDF (194/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
PMON CP-Bit Error Count Register - LSB (Address = 0x1159)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_CP-Bit_Error_Count_Lower_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
REV. 1.0.0
BIT 0
RUR
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
PMON_CP-Bit
Error_Count_Lower
Byte[7:0]
RUR
Performance Monitor - CP Bit Error Count - Lower Byte:
These RESET-upon-READ bits, along with that within the PMON
CP-Bit Error Count Register - MSB combine to reflect the cumu-
lative number of CP bit errors that have been detected by the
Receive DS3 Framer block, since the last read of this register.
This register contains the Least Significant byte of this 16-bit
expression.
NOTE: These register bits are only active if the XRT79L71 has
been configured to operate in the DS3 C-Bit Parity
Framing Format.
PLCP PROCESSOR BLOCK PERFORMANCE MONITOR REGISTERS
A NOTE ABOUT READING OUT THE CONTENTS OF THE PLCP PROCESSOR BLOCK PERFORMANCE
MONITOR REGISTERS
These particular PMON Registers (below) are 16-bit RESET-upon-READ registers. However, the manner in
which these PMON Registers are to be read is listed below.
As mentioned earlier, these PMON Registers are 16-bits in length. More specifically each of these PMON
Registers will consist of a MSB (Most Significant Byte) 8-bit register, and a LSB (Least Significant Byte)
register. Since the Microprocessor Interface of the XRT79L71 contains an eight-bit wide bi-directional data
bus, the user will have to execute two consecutive read operations in order to obtain the full 16-bit content of a
given PMON register. As the user reads out the contents of these PMON Registers, the user must be aware of
the following restrictions.
• During the first (of the two) read operations (to a given PMON Register), the user MUST read out the MSB
Register.
• During the second (of the two) read operations (to a given PMON Register), the user MUST read out the LSB
Register.
NOTE: In contrast to the DS3/E3 Framer Block PMON Registers, the PMON Holding Register is NOT used when reading
out the PLCP Processor Block PMON Registers.
• This method for reading out the PLCP Processor Block PMON Registers, applies to the following PMON
Registers.
a. PMON PLCP BIP-8 Error Count Registers
b. PMON PLCP Framing Byte Error Count Registers
c. PMON PLCP FEBE Event Count Register
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