XRT79L71_1 Datasheet, PDF (111/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Receive E3 Configuration and Status Register # 1 - G.832 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxPLDType[2:0]
RxFERF
Algo.
RxTMark
Algo
RxPLDTypeExp[2:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
1
0
BIT NUMBER
NAME
7-5
RxPLDType[2:0]
4
RxFERF Algo
3
RxTMark Algo
2-0
RxPLDTypExp[2:0]
TYPE
R/O
R/W
R/W
R/W
DESCRIPTION
Received PLD (Payload) Type[2:0]:
These three READ-ONLY bit-fields reflect the value of the Pay-
load Type bits, within the MA byte of the most recently received
E3 frame.
Receive FERF/RDI Defect Declaration/Clearance Algorithm:
This READ/WRITE bit-field permits the user to select a FERF/
RDI Defect Declaration and Clearance Algorithm, as indicated
below.
0 - Configures the Receive E3 Framer block to declare the
FERF/RDI defect condition anytime it receives the FERF/RDI
indicator (within the incoming E3 data-stream) in 3 consecutive
E3 frames. Additionally, this same setting will also configure the
Receive E3 Framer block to clear the FERF/RDI defect condition
anytime it ceases to receive the FERF/RDI indicator (within the
E3 data-stream) for 3 consecutive E3 frames.
1 - Configures the Receive E3 Framer block to declare the
FERF/RDI defect condition anytime it receives the FERF indica-
tor (within the incoming E3 data-stream) in 5 consecutive E3
frames. Additionally, this same setting will also configure the
Receive E3 Framer block to clear the FERF/RDI defect condition
anytime it ceases to receive the FERF indicator for 5 consecu-
tive E3 frames.
Receive Timing Marker Validation Algorithm:
This READ/WRITE bit-field permits the user to select the
Receive Timing Marker Validation algorithm, as indicated below.
0 - The Timing Marker will be validated if it is of the same state
for three (3) consecutive E3 frames.
1 - The Timing Marker will be validated if it is of the same state
for five (5) consecutive E3 frames.
Receive PLD (Payload) Type - Expected:
This READ/WRITE bit-field permits the user to specify the
expected value for the Payload Type, within the MA bytes of
each incoming E3 frame. If the Receive E3 Framer block
receives a Payload Type that differs then what has been written
into these register bits, then it will generate the Payload Type
Mismatch Interrupt.
102