XRT79L71_1 Datasheet, PDF (348/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
3
Transmit Cell Extraction
Memory Overflow
Interrupt Status
2
Transmit Cell Insertion
Memory Overflow
Interrupt Status
1
Detection of HEC Byte
Error Interrupt
TYPE
RUR
RUR
RUR
DESCRIPTION
Transmit Cell Extraction Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit Cell Extraction Memory Overflow Interrupt has
occurred since the last read of this register.
The Transmit ATM Cell Processor block will generate this inter-
rupt anytime an overflow event has occurred in the Transmit Cell
Extraction Memory Buffer.
0 - Indicates that the Transmit ATM Cell Processor block has
NOT declared the Transmit Cell Extraction Memory Overflow
Interrupt since the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the Transmit Cell Extraction Memory Overflow interrupt
since the last read of this register.
Transmit Cell Insertion Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit Cell Insertion Memory Overflow Interrupt has occurred
since the last read of this register.
The Transmit ATM Cell Processor block will generate this inter-
rupt anytime an overflow event has occurred in the Transmit Cell
Insertion Memory Buffer.
0 - Indicates that the Transmit ATM Cell Processor block has
NOT declared the Transmit Cell Insertion Memory Overflow
interrupt since the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the Transmit Cell Insertion Memory Overflow interrupt
since the last read of this register.
Detection of HEC Byte Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
Transmit ATM Cell Processor block has declared the Detection
of HEC Byte Error Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this inter-
rupt anytime it has received an ATM cell (from the TxFIFO) that
contains a HEC byte error.
0 - Indicates that the Transmit ATM Cell Processor block has
NOT declared the Detection of HEC Byte Error Interrupt since
the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the Detection of HEC Byte Error Interrupt since the last
read of this register.
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