XRT79L71_1 Datasheet, PDF (107/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
3
Change of FERF/RDI
Defect Condition Inter-
rupt Status
2
Detection of BIP-4 Error
Interrupt Status
1
Detection of FAS Bit
Error Interrupt Status
0
Unused
TYPE
RUR
RUR
RUR
R/O
DESCRIPTION
Change of FERF/RDI Defect Condition Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
Change in FERF/RDI Defect Condition interrupt has occurred
since the last read of this register.
The Receive DS3/E3 Framer block generates this interrupt in
response to either of the following events.
• Whenever the Receive DS3/E3 Framer block declares the
FERF/RDI Defect condition.
• Whenever the Receive DS3/E3 Framer block clears the
FERF/RDI Defect condition.
0 - Indicates that the Change in FERF/RDI Defect Condition
interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change in FERF/RDI Defect Condition
interrupt has occurred since the last read of this register.
Detection of BIP-4 Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
Detection of BIP-4 Error interrupt has occurred since the last
read of this register.
The Receive DS3/E3 Framer block generates this interrupt any-
time it detects BIP-4 errors within the incoming E3 data-stream.
0 - Indicates that the Detection of BIP-4 Error Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Detection of BIP-4 Error Interrupt has
occurred since the last read of this register.
Detection of FAS Bit Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
Detection of FAS Bit Error interrupt has occurred since the last
read of this register.
The Receive DS3/E3 Framer block generates this interrupt any-
time it detects FAS bit errors within the incoming E3 data-stream.
0 - Indicates that the Detection of FAS Bit Error Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Detection of FAS Bit Error Interrupt has
occurred since the last read of this register.
Receive E3 LAPD Control Register - G.751 (Address = 0x1118)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxLAPD
Any
Unused
R/W
R/O
R/O
R/O
R/O
0
0
0
0
0
BIT 2
Receive
LAPD
Enable
R/W
0
BIT 1
Receive
LAPD
Interrupt
Enable
R/W
0
BIT 0
Receive
LAPD
Interrupt
Status
RUR
0
98