XRT79L71_1 Datasheet, PDF (137/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Transmit DS3 FEAC Configuration and Status Register (Address = 0x1131)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
TxFEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
R/O
R/O
R/O
R/W
RUR
R/W
0
0
0
0
0
0
BIT 1
TxFEAC Go
R/W
0
BIT 0
TxFEAC
Busy
R/O
0
BIT NUMBER
NAME
7-5
Unused
4
TxFEAC Interrupt Enable
3
TxFEACInterrupt Status
2
TxFEACEnable
TYPE
R/O
R/W
RUR
R/W
DESCRIPTION
Please set to "0" for normal operation.
Transmit FEAC Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Transmit FEAC Interrupt. If the user enables this
interrupt, then the Transmit FEAC Controller block will generate
an interrupt, once it has completed its 10th transmission of a
given FEAC Message to the remote terminal equipment.
0 - Disables the Transmit FEAC Interrupt.
In this configuration setting, the Transmit FEAC Controller block
will NOT generate an interrupt after it has completed its 10th
transmission of a given FEAC Message.
1 - Enables the Transmit FEAC Interrupt.
In this configuration setting, the Transmit FEAC Controller block
will generate an interrupt after it has completed its 10th transmis-
sion of a given FEAC Message.
NOTE: This bit-field is only active if Bit 2 (TxFEAC Enable) within
this register is set to "1".
Transmit FEAC Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit FEAC Interrupt has occurred since the last read of this
register, as described below.
0 - Indicates that the Transmit FEAC Interrupt has NOT occurred
since the last read of this register.
1 - Indicates that the Transmit FEAC Interrupt has occurred
since the last read of this register.
NOTE: This bit-field is only active if Bit 2 (TxFEAC Enable) within
this register is set to "1".
Transmit FEAC Controller Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Transmit FEAC Controller block, as described below.
0 - Disables the Transmit FEAC Controller block.
1 - Enables the Transmit FEAC Controller block.
128