XRT79L71_1 Datasheet, PDF (55/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
0
Receive Level 2 Mode
TYPE
R/W
DESCRIPTION
Receive POS-PHY Level 2, Packet Mode:
This READ/WRITE bit-field along with Bits 1 and 0
(Receive_Mode[1:0]) within the Receive POS-PHY Interface -
Receive Control Register - Byte 1 (Address 0x0501) permits the
user to configure the Receive POS-PHY Interface block to oper-
ate in any of the following modes.
• The Level 2, Packet Mode
• The Level 2, Chunk Mode
• The Level 3, Packet Mode
• The Level 3
• Chunk Mode
The following table presents the relationship between these
three bits, and the corresponding operating mode of the Receive
POS-PHY Interface block.
Receive Mode[1:0] Receive Level 2 Mode Resulting Mode of Operation
00
X
Level 2, Chunk Mode
01
X
Level 3, Chunk Mode
10
0
Level 3, Packet Mode
XX
1
Level 2, Packet Mode
A brief description of the Receive POS-PHY Level 2 and Level 3
Modes are presented below.
If the Receive POS-PHY Interface block is configured to
operate in the POS-PHY Level 2 Mode
If the Receive POS-PHY Interface block is configured to operate
in the POS-PHY Level 2 Mode, then all of the following are true.
• When polling, the Receive POS-PHY Interface block will drive
the RxPPA output pin to the appropriate level (reflecting the
RxFIFO fill-status) within ONE RxPClk period (in lieu of two
RxPClk periods) after sampling a given POS-PHY Port
Address via the RxPAddr[4:0] input pins.
• The Link Layer Processor must employ Out-of-Band
Addressing whenever it wishes to perform a Select to READ
operation with the Receive POS-PHY Interface block. In
contrast to the POS-PHY Level 3 Mode, this means that the
Link Layer Processor will function as the POS-PHY Bus
Master for all operations (including Select to READ).
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