XRT79L71_1 Datasheet, PDF (257/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
7-0
Receive UDF3 Byte[7:0]
TYPE
R/W
DESCRIPTION
Receive UDF3 Byte[7:0]:
These READ/WRITE bit-fields permit the user to specify the
value of the UDF3 byte, within any ATM Cell data that is written
to the Receive FIFO and is ultimately output via the Receive
UTOPIA Interface block.
NOTE: These register bits are only valid if the Receive UTOPIA
Interface has been configured to operate in the UTOPIA
Level 3 Mode, and if the Cell Size (as processed via the
Receive UTOPIA Interface) is configured to be 56 bytes.
Receive ATM Cell Processor Block - UDF4 Byte Value Register (Address = 0x171B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Receive UDF4 Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
R/W
0
BIT NUMBER
NAME
7-0
Receive UDF4 Byte[7:0]
TYPE
R/W
DESCRIPTION
Receive UDF4 Byte[7:0]:
These READ/WRITE bit-fields permit the user to specify the
value of the UDF4 byte, within any ATM Cell data that is written
to the Receive FIFO and is ultimately output via the Receive
UTOPIA Interface block.
NOTE: These register bits are only valid if the Receive UTOPIA
Interface has been configured to operate in the UTOPIA
Level 3 Mode, and if the Cell Size (as processed via the
Receive UTOPIA Interface) is configured to be 56 bytes.
Receive ATM Cell Processor Block - Receive Test Cell Header Byte - Byte 1 (Address = 0x1720)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Test Cell Header Byte 1[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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