XRT79L71_1 Datasheet, PDF (210/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
Receive PLCP Processor - Interrupt Status Register (Address = 0x1192)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
BIT 1
Change in
PLCP OOF
Defect
Condition
Interrupt
Status
RUR
0
BIT 0
Change in
PLCP LOF
Defect
Condition
Interrupt
Status
RUR
0
BIT NUMBER
NAME
7-2
Unused
1
Change in PLCP OOF
Defect Condition Inter-
rupt Status
0
Change in PLCP LOF
Defect Condition Inter-
rupt Status
TYPE
R/O
RUR
RUR
DESCRIPTION
Change in PLCP OOF (Out of Frame) Defect Condition Inter-
rupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in PLCP OOF Defect Condition Interrupt has occurred
since the last read of this register, as described below.
0 - The Change in PLCP OOF Defect Condition Interrupt has
NOT occurred since the last read of this register.
1 - The Change in PLCP OOF Defect Condition Interrupt has
occurred since the last read of this register.
NOTE: This bit-field is ONLY ACTIVE if the XRT79L71 has been
configured to operate in BOTH the ATM UNI and the
PLCP Modes.
Change in PLCP LOF (Loss of Frame) Defect Condition
Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in PLCP LOF Defect Condition Interrupt has occurred
since the last read of this register, as described below.
0 - The Change in PLCP LOF Defect Condition Interrupt has
NOT occurred since the last read of this register.
1 - The Change in PLCP LOF Defect Condition Interrupt has
occurred since the last read of this register.
NOTE: This bit-field is ONLY ACTIVE if the XRT79L71 has been
configured to operate in BOTH the ATM UNI and the
PLCP Modes.
Transmit PLCP Processor - A1 Byte Error Mask Register (Address = 0x1198)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
TxPLCP_A1_Byte_Mask[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT 1
R/W
0
BIT 0
R/W
0
201