XRT79L71_1 Datasheet, PDF (432/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
1
TxFIFO Underflow Inter-
rupt Status
0
Transmit POS-PHY Par-
ity Error Interrupt Status
TYPE
RUR
RUR
DESCRIPTION
TxFIFO Underflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
TxFIFO Underflow Interrupt has occurred since the last read of
this register, as described below.
0 - Indicates that the TxFIFO Underflow Interrupt has not
occurred since the last read of this register.
1 - Indicates that the TxFIFO Underflow Interrupt has occurred
since the last read of this register.
NOTE: The Transmit PPP Packet Processor block will generate
the TxFIFO Underflow Interrupt, if it is allowed to deplete
the TxFIFO while the Link Layer Processor is in the
midst of transmitting a PPP Packet to the Transmit POS-
PHY Interface. If the TxFIFO becomes depleted before
the Link Layer Processor was able to complete its
transmission of a given packet, then all of the following
events will occur.
a. The Transmit PPP Packet Processor block will generate
the TxFIFO Underflow Interrupt.
b. That portion of the PPP Packet, that was written into the
Transmit POS-PHY Interface (and in-turn the TxFIFO)
prior to the TxFIFO Underflow event, will be transmitted as
an Aborted packet.
c. That portion of the PPP Packet, that is to be written after
the TxFIFO Underflow event will be discarded.
Transmit POS-PHY Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit POS-PHY Parity Error Interrupt has occurred since the
last read of this register, as described below.
0 - Indicates that the Transmit POS-PHY Parity Error Interrupt
has NOT occurred since the last read of this register.
1 - Indicates that the Transmit POS-PHY Parity Error Interrupt
has occurred since the last reads of this register.
Transmit PPP Packet Processor - Interrupt Enable Register (Address = 0x1F0F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
TxFIFO
Underflow
Interrupt
Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
BIT 0
Transmit
POS-PHY
Parity Error
Interrupt
Enable
R/W
0
BIT NUMBER
NAME
7-2
Unused
TYPE
R/O
DESCRIPTION
423