XRT79L71_1 Datasheet, PDF (122/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
6
Change in Receive Trail-
Trace Message Interrupt
Status
5
Unused
4
Detection of FEBE/REI
Event Interrupt Status
3
Change in FERF/RDI
Defect Condition Inter-
rupt Status
TYPE
RUR
R/O
RUR
RUR
DESCRIPTION
Change in Receive Trail-Trace Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in Receive Trail-Trace Message Interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive Trail-Trace Message
Controller block will generate an interrupt anytime it receives a
Trail-Trace Message, that is different from that of the previously
received message.
0 - Indicates that the Change in Receive Trail-Trace Message
Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change in Receive Trail-Trace Message
Interrupt has occurred since the last read of this register.
NOTE:
The user can obtain the value of the most recently
received Trail-Trace Message by reading out the
contents of the Receive E3 Trail-Trace Message
Register Byte -0 through Receive E3 Trail-Trace
Message Byte -15 registers (Address = 0x111C through
0x112B).
Detection of FEBE/REI Event Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of FEBE Event Interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate an interrupt anytime is detects a FEBE event in the
incoming E3 data-stream.
0 - Indicates that the Detection of FEBE Event Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Detection of FEBE Event Interrupt has
occurred since the last read of this register.
Change in FERF/RDI (Far-End Receive Failure) Defect Con-
dition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in FERF/RDI Defect Condition Interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate an interrupt in response to the following events.
• Whenever the Receive E3 Framer block declares the FERF/
RDI defect condition.
• Whenever the Receive E3 Framer block clears the FERF/RDI
defect condition.
0 - Indicates that the Change in FERF/RDI Defect Condition
Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change in FERF/RDI Defect Condition
Interrupt has occurred since the last read of the register.
NOTE: The user can obtain the state of the FERF/RDI condition,
by reading out the contents of Bit 0 (FERF/RDI Defect
Condition Declared) within the Receive E3 Configuration
and Status Register # 2 - G.832 (Address = 0x1111).
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