XRT79L71_1 Datasheet, PDF (75/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
2
Frame Format
1-0
TimRefSel[1:0]
TYPE
R/W
DESCRIPTION
Frame Format:
This READ/WRITE bit-field, along with Bit 6 (IsDS3), permits the
user to configure the both the Receive DS3/E3 Framer and the
Transmit DS3/E3 Framer blocks to operate in the appropriate
framing format. The relationship between the state of this bit-
field, Bit 2 and the resulting framing format is presented below.
Bit 6 (IsDS3)
Bit 2 (Frame
Format)
0
0
0
1
1
0
1
1
Framing Format
E3, ITU-T G.751
E3, ITU-T G.832
DS3, C-bit Parity
DS3, M13
R/W
NOTE: These bit settings also configure the Transmit DS3/E3
LIU and Receive DS3/E3 LIU Blocks into either the DS3
or E3 Modes.
Time Reference Select:
These two READ/WRITE bit-fields permit the user to define both
the timing source and the framing-alignment source for the
Transmit DS3/E3 Framer block, as presented below.
TimRefSel[1:0]
Timing Reference
00
Loop-Timing (Transmit
DS3/E3 Framer block
timing is taken from the
Receive DS3/E3 LIU
block)
Framing Reference
The Transmit DS3/E3
Framer block will initiate
the generation of a given
"outbound" DS3/E3 frame,
based upon a clock signal
that is asynchronous with
respect to any externally
supplied signal
01
The TxInClk input pin will The Transmit DS3/E3
function as the Timing
Framer block will generate
Source for the Transmit a new DS3/E3 frame upon
DS3/E3 Framer block
the rising edge of the
The Transmit DS3/E3
TxFrameRef Input
Framer block will generate
a new DS3/E3 frame upon
the rising edge of the
TxFrameRef Input
10
The TxInClk input pin will Asynchronous
function as the Timing
Source for the Transmit
DS3/E3 Framer block
11
The TxInClk input pin will Asynchronous
function as the Timing
Source for the Transmit
DS3/E3 Framer block
66