XRT79L71_1 Datasheet, PDF (363/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 3 (Address = 0x1F1A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Header Byte 3 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Idle Cell Header
Byte - 3 [7:0]
TYPE
R/W
DESCRIPTION
Transmit Idle Cell Header Byte - 3[7:0]:
These READ/WRITE register bits, along with that in Transmit
ATM Cell Processor Block - Transmit ATM Idle Cell Header
Bytes 1, 2 and 4 registers permit the user to define the header
byte pattern of all Idle Cells that are generated by the Transmit
ATM Cell Processor block.
This register permits the user to define/specify the value of
Header Byte # 3 within each Idle Cell that is generated and
transmitted by the Transmit ATM Cell Processor block.
Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 4 (Address = 0x1F1B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Header Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit Idle Cell Header
Byte - 4 [7:0]
TYPE
R/W
DESCRIPTION
Transmit Idle Cell Header Byte - 4[7:0]:
These READ/WRITE register bits, along with that in Transmit
ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte
1 through Byte 3 registers permit the user to define the header
byte pattern of all Idle Cells that are generated by the Transmit
ATM Cell Processor block.
This register permits the user to define/specify the value of
Header Byte # 4 within each Idle Cell that is generated and
transmitted by the Transmit ATM Cell Processor block.
354