XRT79L71_1 Datasheet, PDF (38/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
0
Transmit ATM Cell/PPP
Processor Block
Interrupt Status
TYPE
R/O
DESCRIPTION
Receive ATM Cell/PPP Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a Receive
ATM Cell/PPP Processor Block Interrupt is awaiting service.
0 - No Receive ATM Cell/PPP Processor block interrupt is await-
ing service.
1 - At least one Receive ATM Cell/PPP Processor block interrupt
is awaiting service.
Operation Interrupt Enable Register - Byte 1 (Address = 0x0116)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
DS3/E3
LIU/JA Block
Interrupt
Enable
DS3/E3
Framer
Block Inter-
rupt Enable
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
BIT 1
BIT 0
Unused
R/O
R/O
0
0
BIT NUMBER
NAME
7-4
Unused
3
DS3/E3 LIU/JA
Block Interrupt Enable
2
DS3/E3 Framer Block
Interrupt Enable
1-0
Unused
TYPE
DESCRIPTION
R/W DS3/E3 LIU/Jitter Attenuator Block Interrupt Enable:
This READ/WRITE bit permit the user to either enable or disable
the DS3/E3 LIU/JA Block for interrupt generation. If the user
writes a "0" to this register bit and disables the DS3/E3 LIU/JA
Block (for interrupt generation), then all DS3/E3 LIU/JA Block
interrupts will be disabled for interrupt generation. If the user
writes a "1" to this register bit, the user will still need to enable
the individual DS3/E3 LIU/JA Block interrupt(s) at the Source
Level in order to enable that particular interrupt.
0 - Disable all DS3/E3 LIU/JA Block interrupts within the device.
1 - Enables the DS3/E3 LIU/JA Block at the Block-Level.
R/W DS3/E3 Framer Block Interrupt Enable:
This READ/WRITE bit permits the user to either enable or dis-
able the DS3/E3 Framer Block for interrupt generation. If the
user writes a "0" to this register bit and disables the DS3/E3
Framer Block (for interrupt generation), then all DS3/E3 Framer
Block interrupts will be disabled for interrupt generation. If the
user writes a "1" to this register bit, the user will still need to
enable the individual DS3/E3 Framer Block interrupt(s) at the
Source Level in order to enable that particular interrupt.
0 - Disable all DS3/E3 Framer Block interrupts within the device.
1 - Enables the DS3/E3 Framer Block at the Block-Level.
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