XRT79L71_1 Datasheet, PDF (77/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Framer Block Interrupt Enable Register (Address = 0x1104)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Receive
DS3/E3
Framer
Block
Interrupt
Enable
Receive
PLCP
Processor
Block
Interrupt
Enable
Unused
R/W
R/O
R/O
R/O
R/O
0
0
0
0
0
BIT 2
R/O
0
BIT 1
Transmit
DS3/E3
Framer
Block
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
R/W
0
BIT NUMBER
NAME
7
Receive DS3/E3 Framer
Block Interrupt Enable
6
Receive PLCP Processor
Block Interrupt Enable
5-2
Unused
TYPE
R/W
R/W
R/O
DESCRIPTION
Receive DS3/E3 Framer Block Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable
the Receive DS3/E3 Framer block for Interrupt Generation. If
the user enables the Receive DS3/E3 Framer block (for Interrupt
Generation) at the block level, the user still needs to enable the
interrupts at the Source level, in order for these interrupts to be
enabled.
However, if the user disables the Receive DS3/E3 Framer block
(for Interrupt Generation) at the Block Level, then ALL Receive
DS3/E3 Framer block-related interrupts are disabled.
0 - The Receive DS3/E3 Framer block is Disabled for Interrupt
Generation.
1 - The Receive DS3/E3 Framer block is enabled (at the Block
level) for Interrupt Generation.
Receive PLCP Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable
the Receive PLCP Processor block for Interrupt Generation. If
the user enables the Receive PLCP Processor block (for Inter-
rupt Generation) at the block level, the user will still need to
enable the individual interrupts at the Source Level, as well, in
order for these interrupts to be enabled.
However, if the user disables the Receive PLCP Processor block
(for Interrupt Generation) at the Block Level, then ALL Receive
PLCP Processor block-related interrupts are disabled.
0 - The Receive PLCP Processor block is disabled for Interrupt
Generation.
1 - The Receive PLCP Processor block is enabled for Interrupt
Generation.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the ATM/PLCP Mode.
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