XRT79L71_1 Datasheet, PDF (88/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
0
Detection of P-Bit Error
Interrupt Enable
TYPE
R/W
DESCRIPTION
Detection of P-Bit Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Detection of CP-Bit Error Interrupt, within the
XRT79L71. If the user enables this interrupt, then the Receive
DS3/E3 Framer block will generate an interrupt anytime it
detects CP bit errors.
0 - Disables the Detection of CP Bit Error Interrupt.
1 - Enables the Detection of CP-Bit Error Interrupt.
Receive DS3 Interrupt Status Register (Address = 0x1113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Detection of
CP Bit Error
Interrupt
Status
Change of
LOS Defect
Condition
Interrupt
Status
Change of
AIS Defect
Condition
Interrupt
Status
Change of
DS3 Idle
Condition
Interrupt
Status
Change of
FERF/RDI
Defect
Condition
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
Change of
AIC State
Interrupt
Status
BIT 1
BIT 0
Change of
OOF Defect
Condition
Interrupt
Status
Detection of
P-Bit Error
Interrupt
Status
RUR
0
RUR
0
RUR
0
BIT NUMBER
NAME
7
Detection of CP Bit Error
Interrupt Status
6
Change of LOS Defect
Condition Interrupt Status
TYPE
RUR
RUR
DESCRIPTION
Detection of CP-Bit Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Detection of CP-Bit Error Interrupt has occurred since the last
read of this register as depicted below.
0 - The Detection of CP-Bit Error Interrupt has not occurred
since the last read of this register.
1 - The Detection of CP-Bit Error Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the DS3, C-bit Parity Framing
Format.
Change in LOS Defect Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
Change in LOS Defect Condition Interrupt has occurred since
the last read of this register as debicted below.
0 - The Change in LOS Defect Condition Interrupt has not
occurred since the last read of this register.
1 - The Change in LOS Defect Condition Interrupt has occurred
since the last read of this register.
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