XRT79L71_1 Datasheet, PDF (173/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
0
TxN
NAME
TYPE
R/W
DESCRIPTION
Transmit N Bit:
This READ/WRITE bit-field permits the user to control the state
of the N bit, within each Outbound E3 frame, as indicated below.
0 - Forces each N bit (within the Outbound E3 frame) to "0".
1 - Forces each N bit (within the Outbound E3 frame) to "1".
NOTE: This bit-field is only valid if the Transmit E3 Framer block
has been configured to use this bit-field as the source of
the N bit (e.g., if TxNSrcSel[1:0] = "0, 0").
Transmit E3 FAS Error Mask Upper Register - G.751 (Address = 0x1148)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
TxFAS_Error_Mask_Upper[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
R/W
0
BIT NUMBER
NAME
7-5
Unused
4-0
TxFAS_Error_Mask_Upp
er[4:0]
TYPE
R/O
R/W
DESCRIPTION
TxFAS Error Mask Upper[4:0]:
These READ/WRITE bit-fields permit the user to insert bit errors
into the upper five bits, within the FAS (Framing Alignment Sig-
nal), within the outbound E3 data stream.
The Transmit E3 Framer block will perform an XOR operation
with the contents of these FAS bits, and this register. The results
of this calculation will be inserted into the upper 5 FAS bit posi-
tions within the Outbound E3 data stream. For each bit-field
(within this register) that is set to "1", the corresponding bit,
within the FAS will be in error.
NOTE: For normal operation, the user should set this register to
0x00.
Transmit E3 FAS Error Mask Lower Register - G.751 (Address = 0x1149)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
TxFAS_Error_Mask_Lower[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
R/W
0
BIT NUMBER
NAME
7-5
Unused
TYPE
R/O
DESCRIPTION
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