XRT79L71_1 Datasheet, PDF (247/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
4
Receive Cell Extraction
Memory RESET*
3
Receive Cell Extraction
CLAV
2
Receive Cell Insertion
Memory RESET*
TYPE
R/W
R/O
R/W
DESCRIPTION
Receive Cell Extraction Memory RESET*:
This READ/WRITE bit-field permits the user to perform a RESET
operation to the Receive Cell Extraction Memory.
If the user writes a "1" to "0" transition into this bit-field, then the
following events will occur.
a. All of the contents of the Receive Cell Extraction Memory
will be flushed.
b. All READ and WRITE pointers will be reset to their default
positions.
NOTE: Following this RESET event, the user must write the
value "1" into this bit-field in order to enable normal
operation within the Receive Cell Extraction Memory
Receive Cell Extraction Memory - Cell Available Indicator:
This READ-ONLY bit-field indicates whether or not there is at
least ATM cell of data (residing within the Receive Cell Extrac-
tion Memory) that needs to be read out via the Microprocessor
Interface.
0 - Indicates that the Receive Cell Extraction Memory is empty
and contains no ATM cell data.
1 - Indicates that the Receive Cell Extraction Memory contains at
least one ATM cell of data that needs to be read out.
NOTE: The user should validate each ATM cell that is being read
out from the Receive Cell Extraction memory by
checking the state of this bit-field prior to reading out the
contents of any ATM cell data residing within the
Receive Cell Extraction Memory.
Receive Cell Insertion Memory RESET*:
This READ/WRITE bit-field permits the user to perform a RESET
operation to the Receive Cell Insertion Memory.
If the user writes a "1" to "0" transition into this bit-field, then the
following events will occur.
a. All of the contents of the Receive Cell Insertion Memory
will be flushed.
b. All READ and WRITE pointers will be reset to their default
positions.
NOTE: Following this RESET event, the user must write the
value "1" into this bit-field in order to enable normal
operation of the Receive Cell Insertion Memory.
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