XRT79L71_1 Datasheet, PDF (353/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
2
Transmit Cell Insertion
Memory RESET*
1
Transmit Cell Insertion
Memory ROOM
0
Transmit Cell Insertion
Memory WSOC
TYPE
R/W
R/O
W/O
DESCRIPTION
Transmit Cell Insertion Memory RESET*:
This READ/WRITE bit-field permits the user to perform a RESET
operation to the Transmit Cell Insertion Memory.If the user writes
a "1" to "0" transition into this bit-field, then the following events
will occur.
a. All of the contents of the Transmit Cell Insertion Memory
will be flushed.
b. All READ and WRITE pointers will be reset to their default
positions.
NOTE: Following this RESET event, the user must write the
value "1" into this bit-field in order to enable normal
operation of the Transmit Cell Insertion Memory.
Transmit Cell Insertion Memory - ROOM Indicator:
This READ-ONLY bit-field indicates whether or not there is room
(e.g., empty space) available for the contents of another ATM
cell to be written into the Transmit Cell Insertion Memory.
0 - Indicates that the Transmit Cell Insertion Memory does not
contain enough empty space to receive another ATM cell via the
Microprocessor Interface.
1 - Indicates that the Transmit Cell Insertion Memory does con-
tain enough empty space to receive another ATM cell via the
Microprocessor Interface.
NOTE:
The user should verify that the Transmit Cell Insertion
Memory has sufficient empty space to accept another
ATM cell of data (via the Microprocessor Interface) by
polling the state of this bit-field prior to writing each cell
into the Transmit Cell Insertion Memory.
Transmit Cell Insertion Memory - Write SOC (Start of Cell):
Whenever the user is writing the contents of an ATM cell into the
Transmit Cell Insertion Memory, then the user is suppose to
identify/designate the very first byte of this ATM cell by setting
this bit-field to "1". Whenever the user does this, then the Trans-
mit Cell Insertion Memory will know that the next octet that is
written into the Transmit ATM Cell Processor Block - Transmit
Cell Insertion/Extraction Memory Data Register - Byte 3
(Address = 0x1F14) is designated as the first byte of the ATM
cell currently being written into the Transmit Cell Insertion Mem-
ory.
This bit-field must be set to "0" during all other WRITE opera-
tions to the Transmit ATM Cell Processor - Transmit Cell Inser-
tion/Extraction Memory Data Register
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