XRT79L71_1 Datasheet, PDF (329/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
7-0
Rx_Good_PPP_Packet_
Count[7:0]
TYPE
RUR
DESCRIPTION
Receive Good PPP Packet Count[31:24]:
These RESET-upon-READ bit-fields, along with that of the
Receive PPP Packet Processor - Good Packet Count Registers
- Bytes 3 through 1 contain a 32-bit expression for the number of
Good PPP Packets that have been received by the Receive PPP
Packet Processor block.
This particular register contains the LSB (Least Significant Byte)
value for this 32-bit expression.
NOTE: The definition of a Good PPP Packet is any incoming
PPP Packet that does not contain any of the following
characteristics.
a. Contains FCS Errors
b. Is a RUNT Packet
c. Is an Aborted Packet.
Receive PPP Packet Processor - FCS Error Count Register - Byte 3 (Address = 0x1714)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FCS_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
BIT NUMBER
NAME
7-0
FCS_Error_Count[31:24]
TYPE
RUR
DESCRIPTION
FCS Error Count[31:24]:
These RESET-upon-READ bit-fields, along with that of the
Receive PPP Packet Processor - FCS Error Count Registers -
Bytes 2 through 0 contain a 32-bit expression for the number of
PPP Packets that have been flagged as containing FCS errors
by the Receive PPP Packet Processor block.
This particular register contains the MSB (Most Significant Byte)
value for this 32-bit expression.
Receive PPP Packet Processor - FCS Error Count Register - Byte 2 (Address = 0x1715)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FCS_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
320