XRT79L71_1 Datasheet, PDF (189/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
REV. 1.0.0
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
e. PMON FEBE Event Count Registers
f. PMON CP-Bit Error Count Registers
g. PRBS Error Count Registers
• This method for reading out the DS3/E3 Framer PMON Register does not apply to the PLCP Processor,
Transmit ATM Cell Processor or Receive ATM Cell Processor PMON registers.
PMON Excessive Zero Count Registers - MSB (Address = 0x114E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_EXZ_Count_Upper_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
BIT NUMBER
NAME
7-0
PMON_EXZ_Count_Upp
er_Byte[7:0]
TYPE
RUR
DESCRIPTION
Performance Monitor - Excessive Zero Event Count - Upper
Byte:
These RESET-upon-READ bits, along with that within the PMON
Excessive Zero Count Register - LSB combine to reflect the
cumulative number of instances that a string of three or more
consecutive zeros (for DS3 applications) or four or more consec-
utive zeros (for E3 applications) has been detected by the
Receive DS3/E3 Framer block since the last read of this register.
This register contains the Most Significant byte of this 16-bit
expression.
PMON Excessive Zero Count Registers - LSB (Address = 0x114F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_EXZ_Count_Lower_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
BIT NUMBER
NAME
7-0
PMON_EXZ_Count_Upp
er_Byte[7:0]
TYPE
RUR
DESCRIPTION
Performance Monitor - Excessive Zero Event Count - Lower
Byte:
These RESET-upon-READ bits, along with that within the PMON
Excessive Zero Count Register - MSB combine to reflect the
cumulative number of instances that a string of three or more
consecutive zeros (for DS3 applications) or four or more consec-
utive zeros (for E3 applications) has been detected by the
Receive DS3/E3 Framer block since the last read of this register.
This register contains the Least Significant byte of this 16-bit
expression.
180