XRT79L71_1 Datasheet, PDF (2/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
• Supports ATM cell payload scrambling
• Detects and removes HDLC flags
• Maps ATM cells into E3 or DS3 frame
• PLCP frame and mapping of ATM cell streams
RECEIVE CELL PROCESSING
• Extraction of ATM cells from PLCP frame or directly
from E3 or DS3 frame
• Termination of PLCP frame
• Supports payload cell de-scrambling
TRANSMIT PACKET PROCESSING
• Inserts PPP packets into data stream
• Maps HDLC data stream directly into DS3 or E3
frame
• Extracts in-band messaging packets
• Supports CRC-16/32, HDLC flag and Idle
sequence generation
RECEIVE PACKET PROCESSING
• Extracts HDLC data stream from DS3 or E3 frame
• Inserts in-band messaging packets
UTOPIA/ SYSTEM INTERFACE
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
• Compliant with ATM Forum UTOPIA II interface
• Programmable FIFO size for both Transmit and
Receive direction
• Compliant to POS-PHY Level 2 interface
SERIAL INTERFACE
• Serial clock and data interface for accessing DS3/
E3 framer
• Serial clock and data interface for accessing cell/
packet processor
APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches
FIGURE 1. BLOCK DIAGRAM OF THE XRT79L71
RTIP
RRING
AGC/
Equalizer
TU-3
PCOloHck ^&
P r o c eDsastoar
Recov ery
Receiver Block
Jitter
Attenuator
Rx DS3/
E3
Framer
TTIP
TRING
E3CLK
DS3CLK
ClkIN
12.288
MHz
Pulse
Shaper
Tim ing
Control
Transmitter Block
Clock
Synthesizer
Jitter
Attenuator
Tx DS3/
E3
F ram er
Microprocessor Interface
PLCP &
Overhead
HDLC
Controller
PLCP &
Overhead
HDLC
Controller
ATM Cell
Processor
or PPP
Processor
UTOPIA/
POS-PHY
Interface
ATM Cell
Processor
or PPP
Processor
2
UTOPIA/
POS-PHY
Interface
JTAG Test Port
Receive
Utopia
POS-PHY
Interface
Tran sm it
Utopia
POS-PHY
Interface
2