XRT79L71_1 Datasheet, PDF (188/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7
TxSSM Enable
R/W Transmit SSM Enable:
This READ/WRITE bit-field permits the user to configure the
Transmit E3 Framer block to operate in either the Old ITU-T
G.832 Framing format or in the New ITU-T G.832 Framing for-
mat, as described below.
0 - Configures the Transmit E3 Framer block to support the Pre
October 1998 version of the E3, ITU-T G.832 framing format. In
this particular setting, the Transmit SSM Controller block will be
disabled.
1 - Configures the Transmit E3 Framer block to support the
October 1998 version of the E3, ITU-T G.832 framing format. In
this particular setting, the Transmit SSM Controller block will be
enabled.
6-4
Unused
R/O
3-0
TxSSM[3:0]
R/W Transmit (or Outbound) Synchronization Status Mes-
sage[3:0]:
These READ/WRITE bit-fields permit the user to specify the con-
tents of the Outbound Synchronization Status Message (SSM)
that is to be transported via the Outbound E3 data-stream. The
Transmit SSM Controller block will then proceed to transport this
SSM via the outbound E3 data-stream.
NOTE: These bit-fields are only active if Bit 7 (TxSSM Enable)
within this register is set to "1".
DS3/E3 FRAMER BLOCK PERFORMANCE MONITOR REGISTERS
A NOTE ABOUT READING OUT THE CONTENTS OF THE DS3/E3 FRAMER BLOCK PERFORMANCE
MONITOR REGISTERS
These particular PMON Registers (below) are 16-bit RESET-upon-READ registers. However, the manner in
which these PMON Registers are to be read is listed below.
As mentioned earlier, these PMON Registers are 16-bits in length. More specifically each of these PMON
Registers will consist of a MSB (Most Significant Byte) 8-bit register, and a LSB (Least Significant Byte)
register. Since the Microprocessor Interface of the XRT79L71 contains an eight-bit wide bi-directional data
bus, the user will have to execute two consecutive read operations in order to obtain the full 16-bit content of a
given PMON register. As the user reads out the contents of these PMON Registers, the user must be aware of
the following restrictions.
• During the first (of the two) read operations (to a given PMON Register), the user can read out either the
MSB or the LSB Register.
• However, as the user executes this first read operation, the entire 16-bit contents of this particular PMON
register will be cleared to "0x0000". The XRT79L71 will store the contents of the un-read register into the
PMON Holding Register (Address = 0x116C).
• Therefore, during the second (of the two) read operations (to a given PMON Register), the user MUST obtain
the contents of the un-read byte, from the PMON Holding Register.
• This method for reading out the PMON Registers, applies to the following PMON Registers.
a. PMON Excessive Zero Count Registers
b. PMON Line Code Violation Count Registers
c. PMON Framing Bit/Byte Error Count Registers
d. PMON Parity/P-Bit Count Registers
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