XRT79L71_1 Datasheet, PDF (347/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Transmit ATM Cell Processor Block - Transmit ATM Interrupt Status Register (Address = 0x1F0B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Transmit Cell
Extraction
Interrupt
Status
Transmit Cell
Insertion
Interrupt
Status
Transmit Cell
Extraction
Memory
Overflow
Interrupt
Status
Transmit Cell
Insertion
Memory
Overflow
Interrupt
Status
Detection of
HEC Byte
Error
Interrupt
Status
Detection of
Transmit
UTOPIA
Parity Error
Interrupt
Status
R/O
R/O
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-6
Unused
5
Transmit Cell Extraction
Interrupt Status
4
Transmit Cell Insertion
Interrupt Status
TYPE
R/O
RUR
RUR
DESCRIPTION
Transmit Cell Extraction Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit Cell Extraction interrupt has occurred since the last
read of this register.
The Transmit ATM Cell Processor block will generate the Trans-
mit Cell Extraction Interrupt anytime it receives an incoming ATM
cell (from the TxFIFO) and loads an ATM cell into the Extraction
Memory Buffer.
0 - Indicates that the Transmit Cell Extraction Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Transmit Cell Extraction Interrupt has
occurred since the last read of this register.
Transmit Cell Insertion Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Transmit Cell Insertion interrupt has occurred since the last read
of this register.
The Transmit ATM Cell Processor block will generate the Trans-
mit Cell Insertion Interrupt anytime a cell (residing in the Trans-
mit Cell Insertion Buffer) is read out of the Transmit Cell Insertion
Buffer and is loaded into the outbound ATM cell traffic.
0 - Indicates that the Transmit Cell Insertion Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Transmit Cell Insertion Interrupt has
occurred since the last read of this register.
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