XRT79L71_1 Datasheet, PDF (56/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
0
Receive Level 2 Mode
(CONTINUED)
TYPE
R/W
DESCRIPTION
If the Receive POS-PHY Interface block is configured to
operate in the Receive POS-PHY Level 3 Mode
If the Receive POS-PHY Interface block is configured to operate
in the POS-PHY Level 3 Mode, then all of the following are true.·
When polling, the Receive POS-PHY Interface block will drive
the RxPPA output pin to the appropriate level (reflecting the
RxFIFO fill-status) within TWO RxPClk periods (in lieu of one
RxPClk periods) after sampling a given POS-PHY Port Address
via the RxPAddr[4:0] input pins.· The Link Layer Processor must
be responsive to In-Band Addressing signals from the Receive
POS-PHY Interface block, anytime it (the Receive POS-PHY
Interface block) wishes to perform Select to READ operations
with the Link Layer Processor. This means that for Select to
READ operations, the Receive POS-PHY Interface (and NOT
the Link Layer Processor) will function as the POS-PHY Bus
Master.
NOTE:
If the user configures the Receive POS-PHY Interface
block to operate in the POS-PHY Level 3 Mode, then
(for Multi-PHY Applications) the Receive POS-PHY
Interface (and NOT the Link Layer Processor) will
function as the POS-PHY Bus Master, particular during
Select to READ Operations. As a consequence, if the
user plans to design the XRT79L71 in a PPP
Applications, in which multiple PHY-Layer devices will
share a common POS-PHY Bus, then the user is
strongly advised to ONLY configure the Receive POS-
PHY Interface (within the XRT79L71) to operate in the
POS-PHY Level 2 Mode. The XRT79L71 does not
contain any hooks to support any sort of POS-PHY
Arbitration Scheme if it is configured to operate in the
POS-PHY Level 3 Mode.
Receive POS-PHY Interface - Receive Control Register Byte - 1 (Address = 0x0501)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Chunk_Size[2:0]/
RxFIFO_Packet_Fill_Level[2:0]
Receive POS-PHY Data
Bus Width[1:0]
Receive Mode[1:0]
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7
Unused
TYPE
R/O
DESCRIPTION
47