TDA3MV Datasheet, PDF (99/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.
(8) resetn and porz must remain asserted low for a minimum of 12P⁽¹²⁾ after xi_osc0 is stable at a valid frequency.
(9) Setup time: SYSBOOT[15:0] pins must be valid 2P⁽¹²⁾ before porz is de-asserted high.
(10) Hold time: SYSBOOT[15:0] pins must be valid 15P⁽¹²⁾ after porz is de-asserted high.
(11) resetn to rstoutn delay is 2ms.
(12) * P = 1/(SYS_CLK1/610) frequency in ns.
(13) Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about
voltage levels, refer to Table 5-4, Recommended Operating Conditions.
porz
vddshv1, vddshv2, vddshv3,
vddshv4, vddshv5, vddshv6
vdd_dspeve
vdd
vdds_ddr1, vdds_ddr2, vdds_ddr3
vdda_osc, vdda_per, vdda_ddr_dsp,
vdda_gmac_core, vdda_csi,
vdda_dac, vdda_adc
vdds18v_ddr1, vdds18v_ddr2,
vdds18v_ddr3, vdds18v,
xi_osc0
DSPEVE voltage
CORE voltage
EMIF voltage
Note 3
Note 4
Note 5
Note 6
Note 7
SPRS916_ELCH_02
Figure 5-2. Power-Down Sequencing
(1) Grey shaded areas show valid times to ramp down each supply.
(2) Dashed lines are not valid ramp times but show alternate ramp possibilities based on the associated note.
(3) If any of the vddshv* are used as 1.8V only, then these rails can ramp down at the same time as vdds18v_* or be combined with
vdds18v_*. If vddshv* are used as 3.3V, they can start ramping down no sooner than 100µs after PORz low assertion and must ramped
down before vdd_dspeve. If all vddshv_* are 1.8V, then neither vdd_dspeve or vdd should start ramping down no sooner than 100µs
after PORz low assertion.
(4) vdd_dspeve can ramp down before or at the same time as vdd/vpp.
(5) vdds_ddr* can start ramping down no sooner than 500µs after vdd and must be ramped down before vdds18v. vdds_ddr* can start
ramping down before, concurrently or after vdda_*, there are no dependencies between vdds_ddr* and vdda_* domains.
– vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped
down together for simplified power sequencing.
– If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come down
together or before the vdds18v_* supply. The DDR supply in this case should never ramp down after the vdds18v_*.
(6) vdda_* can ramp down before or at the same time as vdds18v_*.
(7) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(8) Ramped Down is defined as reaching a voltage level of no more than 0.6V.
Figure 5-3 describes vddshv[1-6] supplies falling after vdds18v supplies delta.
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Specifications
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