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TDA3MV Datasheet, PDF (142/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0
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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
I2Ci_SDA
I2Ci_SCL
26
23
19
25
21
20
16
18
27
22
18
17
24
28
Stop
Start
Repeated
Start
Figure 7-21. I2C Transmit Timing
Stop
SPRS91v_I2C_02
7.11 Universal Asynchronous Receiver Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. There are 3 UART modules in the device. Each
UART can be used for configuration and data exchange with a number of external peripheral devices or
interprocessor communication between devices.
The UARTi (where i = 1 to 3) include the following features:
• 16C750 compatibility
• 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
• Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
• Break character detection and generation
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
NOTE
For more information, see the UART section of the Device TRM.
Table 7-17, Table 7-18 and Figure 7-22 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
NO.
PARAMETER
4 tw(RX)
5 tw(CTS)
td(RTS-TX)
td(CTS-TX)
Table 7-17. Timing Requirements for UART
DESCRIPTION
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
MIN
0.96U(1)
0.96U(1)
P(2)
P(2)
MAX
1.05U(1)
1.05U(1)
UNIT
ns
ns
ns
ns
142 Timing Requirements and Switching Characteristics
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