TDA3MV Datasheet, PDF (222/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 8-32. CK and ADDR_CTRL Routing Specification (continued)
NO.
PARAMETER
MIN
MAX
UNIT
RSC210
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽²⁾
3w
(1) Series terminator, if used, should be located closest to the Device.
(2) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) This is the longest routing length of the CK and ADDR_CTRL net classes.
Figure 8-44 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended. The termination resistor should be placed
near the processor.
E0
E1
DDR2 Controller
E2
E3
PCB_DDR2_7
Figure 8-44. DQS and DQ Routing and Topology
Table 8-33. DQS and DQ Routing Specification
NO.
PARAMETER
MIN
MAX
UNIT
RSDQ21 Center-to-center DQS-DQSn spacing in E0|E1|E2|E3
2w
RSDQ22
RSDQ23
RSDQ24
RSDQ25
RSDQ26
RSDQ27
RSDQ28
RSDQ29
RSDQ210
DQS-DQSn skew in E0|E1|E2|E3
Center-to-center DQS to other DDR2 trace spacing⁽¹⁾
DQS/DQ trace length ^(2)(3)(4)
DQ-to-DQS skew mismatch^(2)(3)(4)
DQ-to-DQ skew mismatch^(2)(3)(4)
DQ-to-DQ/DQS via count mismatch^(2)(3)(4)
Center-to-center DQ to other DDR2 trace spacing⁽¹⁾⁽⁵⁾
Center-to-center DQ to other DQ trace spacing^(1)(6)(7)
DQ/DQS E skew mismatch^(2)(3)(4)
5
ps
4w
325
ps
10
ps
10
ps
1
Vias
4w
3w
25
ps
(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data
byte1.
(5) DQs from other DQS domains are considered other DDR2 trace.
(6) DQs from other data bytes are considered other DDR2 trace.
(7) This is the longest routing distance of each of the DQS and DQ net classes.
8.9 DDR3 Board Design and Layout Guidelines
222 Applications, Implementation, and Layout
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