TDA3MV Datasheet, PDF (183/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

www.ti.com
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in Figure 8-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 8-
9 are known as:
• 2-via, Skinny End Exit (2vSEE)
• 2-via, Wide End Exit (2vWEE)
• 2-via, Wide Side Exit (2vWSE)
• 4-via, Wide Side Exit (4vWSE)
• 2-via, In-Pad (2vIP)
Via
Pad
Via-in-pad
Trace
Mounting geometry for reduced inductance
SPRS91v_PCB_FREQ_04
Figure 8-9. Capacitor Placement Geometry for Improved Mounting Inductance
NOTE
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 8-
9).
2. Place Dcaps on "same-side” as component within their power plane outline to minimize "decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
minimum inductance for top vs bottom-side placement.
3. Place Dcaps on "opposite-side” as component within their power plane outline if "same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 183
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA