TDA3MV Datasheet, PDF (220/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
8.8.2.2.8 Net Classes
Table 8-29 lists the clock net classes for the DDR2 interface. Table 8-30 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-29. Clock Net Class Definitions
CLOCK NET CLASS PIN NAMES
CK
ddrx_ck / ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
DQS2⁽¹⁾
DQS3⁽¹⁾
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
(1) Only used on 32-bit wide DDR2 memory systems.
Table 8-30. Signal Net Class Definitions
SIGNAL NET CLASS
ADDR_CTRL
ASSOCIATED CLOCK
NET CLASS
CK
DQ0
DQS0
DQ1
DQ2⁽¹⁾
DQ3⁽¹⁾
DQS1
DQS2
DQS3
(1) Only used on 32-bit wide DDR2 memory systems.
PIN NAMES
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
8.8.2.2.9 DDR2 Signal Termination
Signal terminators are NOT required in CK, ADDR_CTRL, and DATA net classes. Serial terminators may
be used to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are integrated
on the data byte net classes. They should be enabled to ensure signal integrity. Table 8-31 shows the
specifications for the series terminators.
Table 8-31. DDR2 Signal Terminations
NO.
PARAMETER
MIN
ST21
CK net class⁽¹⁾⁽²⁾
0
ST22
ADDR_CTRL net class^{(1) (2)(3)(4)}
0
ST23 Data byte net classes (DQS0-DQS3, DQ0-DQ3)⁽⁵⁾
0
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.
(2) Only required for EMI reduction.
(3) Terminator values larger than typical only recommended to address EMI issues.
(4) Termination value should be uniform across net class.
(5) No external terminations allowed for data byte net classes ODT is to be used.
TYP
MAX
10
Zo
Zo
UNIT
Ω
Ω
Ω
8.8.2.2.10 VREF Routing
VREF (ddrx_vref0) is used as a reference by the input buffers of the DDR2 memories. VREF is intended
to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in
Figure 8-39. Other methods of creating VREF are not recommended. Figure 8-42 shows the layout
guidelines for VREF.
220 Applications, Implementation, and Layout
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA