TDA3MV Datasheet, PDF (187/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
8.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
8.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
8.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in Figure 8-12 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS91v_PCB_EMC_02
Figure 8-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS91v_PCB_EMC_03
Figure 8-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in Figure 8-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
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Applications, Implementation, and Layout 187
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