TDA3MV Datasheet, PDF (117/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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7.6 Imaging Subsystem (ISS)
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
NOTE
For more information, see the Imaging Subsystem chapter of the device TRM.
The imaging subsystem (ISS) deals with the processing of the pixel data coming from an external image
sensor or data from memory (image format encoding and decoding can be done to and from memory).
With its subparts, such as interfaces and interconnects, image signal processor (ISP), and still image
coprocessor (SIMCOP), the ISS is a key component for the following use cases:
• Rear View Camera
• Front View Stereo Camera
• Surround View Camera
The ISS is mainly composed of CAL_A, CAL_B, LVDS-RX camera interfaces, a parallel interface (CPI),
an ISP, and a block-based imaging accelerator (SIMCOP).
• The Camera Adapter Layer (CAL_A) supports MIPI® CSI2 protocol with four data lanes. The CAL_A is
targeted as sensor capture interface and write DMA, while CAL_B is targeted as read DMA engine and
does not support sensor capture.
• The LVDS receiver (LVDS-RX) support Sony / Aptina / Omnivision / Panasonic / AltaSens serial
interfaces.
• The parallel interface (CPI) supports up to 16 data lanes.
All interfaces can use the image signal processor (ISP), but not concurrently. When one interface uses the
ISP, the other must send data to memory. However, the ISP can still be used to process this data in
memory-to-memory. Time multiplex processing is also possible.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in Table 7-6.
In Table 7-6 are presented the specific groupings of signals (IOSET) for use with ISS.
SIGNALS
cpi_pclk
cpi_data0
cpi_data1
cpi_data2
cpi_data3
cpi_data4
cpi_data5
cpi_data6
cpi_data7
cpi_data8
cpi_data9
cpi_data10
cpi_data11
cpi_data12
Table 7-6. Camera Parallel Interface (CPI) IOSETs
BALL
F22
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
J17
K22
K21
IOSET1
MUX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BALL
F22
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
J17
K22
K21
IOSET2
MUX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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Timing Requirements and Switching Characteristics 117
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