TDA3MV Datasheet, PDF (228/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 8-39. Placement Specifications
No.
PARAMETER
MIN
MAX
UNIT
KOD31 X1
1700
Mils
KOD34 Y1
1800
Mils
KOD35 Y2
600
Mils
KOD36 DDR3 keepout
region⁽¹⁾
KOD37 Clearance from non-
4
W
DDR3 signal to
DDR3 keepout
region ⁽²⁾⁽³⁾
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
8.9.2.7 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 8-48. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-
39. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the
two signals from the DDR3 controller should be separated from each other by the specification in Table 8-
39 (see KOD37).
228 Applications, Implementation, and Layout
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