TDA3MV Datasheet, PDF (75/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

www.ti.com
5 Specifications
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
NOTE
For more information, see Power, Reset and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
NOTE
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in
Section 4.4.8, External Memory Interface (EMIF), column "SIGNAL NAME" are not to be
confused with DDR1 type of SDRAM memories.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
5.1 Absolute Maximum Ratings
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those listed under Section 5.4, Recommended Operating Conditions, is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Table 5-1. Absolute Maximum Rating Over Junction Temperature Range
PARAMETER⁽¹⁾
V_SUPPLY (Steady-State)
V_IO (Steady-State)
SR
V_{IO (Transient Overshoot /}
Undershoot)
DESCRIPTION
Supply Voltage Ranges (Steady-
State)
Core (vdd, vdd_dspeve)
Analog (vdda_per, vdda_ddr_dsp,
vdda_gmac_core, vdda_osc,
vdda_csi, vdda_dac, vdda_adc)
vdds_ddr1, vdds_ddr2, vdds_ddr3
(1.35V mode)
vdds_ddr1, vdds_ddr2, vdds_ddr3
(1.5V mode)
vdds18v, vdds18v_ddr1,
vdds18v_ddr2, vdds18v_ddr3
vddshv1-6 (1.8V mode)
vddshv1-6 (3.3V mode)
Input and Output Voltage Ranges
(Steady-State)
Core I/Os
Analog I/Os
I/O 1.35V
I/O 1.5V
1.8V I/Os
3.3V I/Os
Maximum slew rate, all supplies
Input and Output Voltage Ranges (Transient Overshoot / Undershoot)
Note: valid for up to 20% of the signal period
MIN
MAX
-0.3
1.5
-0.3
2.0
-0.3
1.65
-0.3
1.8
-0.3
2.1
-0.3
2.1
-0.3
3.8
-0.3
1.5
-0.3
2.0
-0.3
1.65
-0.3
1.8
-0.3
2.1
-0.3
3.8
10⁵
0.2*VDD
(2)
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V/s
V
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA
Specifications
75