TDA3MV Datasheet, PDF (148/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
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Table 7-21. Timing Requirements for SPI - Slave Mode⁽⁵⁾ (continued)
NO.
SS8 ⁽¹⁾
SS9 ⁽¹⁾
PARAMETER
t_{su(CS-SPICLK)}
t_h(SPICLK-CS)
DESCRIPTION
Setup time, spi_cs[x] valid before spi_sclk first edge
Hold time, spi_cs[x] valid after spi_sclk last edge
MODE
MIN
2.82
2.82
MAX
UNIT
ns
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) P = SPICLK period.
(4) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(5) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
SS3
SS9
spim_sclk(IN) ^POL=0
SS2
SS1
POL=1
SS3
spim_sclk(IN)
spim_d(OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
SS3
SS9
spim_sclk(IN) ^POL=0
SS3
SS1
POL=1
SS2
spim_sclk(IN)
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
SS6
Bit n-3
Bit 1
Bit 0
Figure 7-25. McSPI - Slave Mode Transmit
SPRS91v_McSPI_03
148 Timing Requirements and Switching Characteristics
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