TDA3MV Datasheet, PDF (108/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock , a
96-MHz functional clock to subsystems and peripherals.
• DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.
• DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK
and DSP1_CLK).
• DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its
associated EMIF PHYs.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
• DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
6.2.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.
Table 6-10 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications.
Table 6-10. DPLL Control
DPLL NAME
DPLL_CORE
DPLL_EVE_VID_DSP
DPLL_GMAC_DSP
DPLL_PER
DPLL_DDR
(1) DPLL is in the always-on domain.
CONTROLLED BY PRCM
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Table 6-11 and summarize the DPLL characteristics and assume testing over recommended operating
conditions.
108 Clock Specifications
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