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TDA3MV Datasheet, PDF (150/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0
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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
SIGNALS
spi1_d1
spi1_d0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
spi3_sclk
spi3_d1
spi3_d0
spi3_cs0
BALL
U6
T5
R6
Table 7-22. McSPI1/3 IOSETs (continued)
IOSET1
MUX
0
0
0
BALL
U6
T5
R6
IOSET2
MUX
0
0
0
F14
5
C14
5
SPI3
F15
4
C6
4
D14
4
F7
4
D15
4
E7
4
F16
4
B6
4
BALL
U6
T5
R6
R5
IOSET3
MUX
0
0
0
0
7.13 Quad Serial Peripheral Interface (QSPI)
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
• Programmable clock divider
• Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
• 4 external chip select signals
• Support for 3-, 4- or 6-pin SPI interface
• Programmable CS_N to DOUT delay from 0 to 3 DCLKs
• Programmable signal polarities
• Programmable active clock edge
• Software controllable interface allowing for any type of SPI transfer
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
Table 7-23 and Table 7-24 present Timing and Switching Characteristics for Quad SPI Interface.
No PARAMETER
1
tc(SCLK)
2
tw(SCLKL)
3
tw(SCLKH)
Table 7-23. Switching Characteristics for QSPI
DESCRIPTION
Cycle time, sclk
Pulse duration, sclk low
Pulse duration, sclk high
Mode
Default
Timing
Mode,
Clock
Mode 0
Default
Timing
Mode,
Clock
Mode 3
MIN
10.4
15.625
Y*P-1 (1)
Y*P-1 (1)
MAX
UNIT
ns
ns
ns
ns
150 Timing Requirements and Switching Characteristics
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