TDA3MV Datasheet, PDF (101/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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6 Clock Specifications
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Clock Signals and Clock Management Functional Description section
of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
• The system clocks, SYS_CLK1(Mandatory) and SYS_CLK2(Optional) are the main clock sources of
the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
shows the external input clock sources and the output clocks to peripherals.
DEVICE
rstoutn
resetn
porz
xi_osc0
xo_osc0
xi_osc1
xo_osc1
Warm reset output.
Device reset input.
Power ON Reset.
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
To quartz (from oscillator output).
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
To quartz (from oscillator output).
clkout0
clkout1
clkout2
Output clkout[0:2] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
xref_clk0
xref_clk1
xref_clk2
sysboot[15:0]
External Reference Clock [0:2].
For Audio and other Peripherals
Boot Mode Configuration
6.1 Input Clock Specifications
Figure 6-1. Clock Interface
SPRS91v_CLK_01_SR2.0
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Clock Specifications 101