TDA3MV Datasheet, PDF (158/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
2
1
2
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 0)^(A)
ACLKR/X (CLKRP = CLKXP = 1)^(B)
AFSR/X (Bit Width, 0 Bit Delay)
4
3
4
6
5
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS91v_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 7-31. McASP Input Timing
Table 7-29, Table 7-30, Table 7-31 and Figure 7-32 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP3.
Table 7-29. Switching Characteristics Over Recommended Operating Conditions for McASP1 ⁽¹⁾
NO. PARAMETER DESCRIPTION
9
t_c(AHCLKX)
10
t_w(AHCLKX)
Cycle time, AHCLKX
Pulse duration, AHCLKX high or low
11
t_c(ACLKRX)
12
t_w(ACLKRX)
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
13 t _{d(ACLK-AFSXR)} Delay time, ACLKR/X transmit edge to AFSX/R output
valid
MODE
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
MIN
20
0.5P -
2.5 ⁽²⁾
20
0.5P -
2.5 ⁽³⁾
0
2
MAX
6
22.2
UNIT
ns
ns
ns
ns
ns
ns
158 Timing Requirements and Switching Characteristics
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA