TDA3MV Datasheet, PDF (154/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
PHA=0
cs
POL=0
sclk
Q7
d[0]
Q4
Q1
Q2 Q3
Q9 Q6
Command Command
Bit n-1
Bit n-2
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Q5
Q6
Q6
Q8
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
Figure 7-30. QSPI Write (Clock Mode 0)
SPRS85v_TIMING_OSPI1_04
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module section.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in Table 7-25.
In Table 7-25 are presented the specific groupings of signals (IOSET) for use with QSPI.
SIGNALS
qspi1_sclk
qspi1_rtclk
qspi1_d0
qspi1_d1
qspi1_d2
qspi1_d3
qspi1_cs0
qspi1_cs1
IOSET1
BALL
MUX
C8
1
C14
8
B9
1
F10
1
A9
1
D10
1
E10
1
Table 7-25. QSPI IOSETs
IOSET2
BALL
MUX
C8
1
B7
1
B9
1
F10
1
A9
1
D10
1
E10
1
IOSET3
BALL
MUX
C8
1
F13
5
B9
1
F10
1
A9
1
D10
1
E10
1
F15
5
IOSET4
BALL
MUX
C8
1
D8
2
B9
1
F10
1
A9
1
D10
1
E10
1
154 Timing Requirements and Switching Characteristics
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