TDA3MV Datasheet, PDF (168/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
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Table 7-43. Switching Characteristics for MMC - SD/SDIO Default Speed Mode (continued)
NO.
DS2
PARAMETER
t_w(clkL)
DESCRIPTION
Pulse duration, mmc_clk low
DS3
t_d(clkL-cmdV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
DS4 t_d(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
MIN
0.5*P-
0.270
-14.93
-14.93
MAX
14.93
14.93
UNIT
ns
ns
ns
mmc_clk
mmc_cmd
mmc_dat[3:0]
DS2
DS1
DS0
DS6
DS5
DS8
DS7
Figure 7-37. MMC/SD/SDIOj in - Default Speed - Receiver Mode
SPRS91v_MMC_01
mmc_clk
mmc_cmd
mmc_dat[3:0]
DS2
DS1
DS0
DS3
DS4
Figure 7-38. MMC/SD/SDIOj in - Default Speed - Transmiter Mode
SPRS91v_MMC_02
7.17.2 MMC, SD High Speed
Figure 7-39, Figure 7-40, and Table 7-44 through Table 7-45 present Timing requirements and Switching
characteristics for MMC - SD and SDIO High speed in receiver and transmiter mode.
Table 7-44. Timing Requirements for MMC - SD/SDIO High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
MIN
MAX
5.3
2.6
5.3
2.6
UNIT
ns
ns
ns
ns
168 Timing Requirements and Switching Characteristics
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