TDA3MV Datasheet, PDF (207/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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8.7.3.6 LPDDR2 Net Classes
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 8-18. Clock Net Class Definitions for the LPDDR2 Interface
CLOCK NET CLASS
CK
DQS0
DQS1
DQS2
DQS3
PIN NAMES
ddr1_ck and ddr1_nck
ddr1_dqs0 and ddr1_dqsn0
ddr1_dqs1 and ddr1_dqsn1
ddr1_dqs2 and ddr1_dqsn2
ddr1_dqs3 and ddr1_dqsn3
Table 8-19. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface
SIGNAL NET CLASS
ADDR_CTRL
ASSOCIATED CLOCK
NET CLASS
CK
DQ0
DQ1
DQ2
DQ3
(1) DQ data class includes DQS/N pins
DQS0
DQS1
DQS2
DQS3
BALL NAMES
ddr1_ba[2:0], ddr1_csn0, ddr1_cke0, ddr1_rasn, ddr1_casn, ddr1_wen,
ddr1_a1, ddr1_a2, dr1_a10, ddr1_a13
ddr1_d[7:0], ddr1_dqm0, ddr1_dqs0, ddr1_dqsn0 ⁽¹⁾
ddr1_d[15:8], ddr1_dqm1, ddr1_dqs1, ddr1_dqsn1 ⁽¹⁾
ddr1_d[23:16], ddr1_dqm2, ddr1_dqs2, ddr1_dqsn2 ⁽¹⁾
ddr1_d[31:24], ddr1_dqm3, ddr1_dqs3, ddr1_dqsn3 ⁽¹⁾
8.7.3.7 LPDDR2 Signal Termination
On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for
normal operation. System designers may evaluate the need for additional series termination if required
based on signal integrity, EMI and overshoot/undershoot reduction.
On board series termination is recommended for all ADDR_CTRL and CK class signals. It is
recommended a resistor with value of 10 Ω to be placed close to the TDA3x source pin (within 350 mils).
On board series termination is recommended for all DQx and DQSx class signals. It is recommended a
resistor with value of 22 Ω to be placed close to the TDA3x source pin (within 500 mils).
8.7.3.8 LPDDR2 DDR_VREF Routing
DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory. DDR_VREF is
intended to be half the LPDDR2 power supply voltage and is typically generated with a voltage divider
connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1-
µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate
routing congestion.
8.7.4 Routing Specification
8.7.4.1 DQS[x] and DQ[x] Routing Specification
DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 8-27 and
Figure 8-28 represent the supported topologies. Figure 8-29 and Figure 8-30 show the DQS[x] and DQ[x]
routing. Figure 8-31 shows the DQLM for the LPDDR2 interface.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 207
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